//////////////////////////////////////////ok
#include"stdafx.h"
#include "bochs.h"



void IA32_CPU::SHLD_EwGw(Ia32_Instruction_c *i)
{
  Bit16u op1_16, op2_16, result_16;
  Bit32u temp_32, result_32;
  unsigned count;

  if (i->b1() == 0x1a4)
    count = i->Ib();
  else // 0x1a5
    count = CL;

  count &= 0x1f; // use only 5 LSB's

  if (i->modC0()) 
  {
    op1_16 = IA32_READ_16BIT_REG(i->rm());
  }
  else 
  {
    read_RMW_virtual_word(i->seg(), IA32_RMAddr(i), &op1_16);
  }

  if (!count) 
	  return;

  op2_16 = IA32_READ_16BIT_REG(i->nnn());

  temp_32 = ((Bit32u)(op1_16) << 16) | (op2_16); // double formed by op1:op2
  result_32 = temp_32 << count;

  if (count > 16) 
  {
    result_32 |= (op1_16 << (count - 16));
  }

  result_16 = result_32 >> 16;

  if (i->modC0()) 
  {
    IA32_WRITE_16BIT_REG(i->rm(), result_16);
  }
  else 
  {
    write_RMW_virtual_word(result_16);
  }

  IA32_SET_FLAGS_OSZAPC_16(op1_16, count, result_16, IA32_INSTR_SHL16);
}

void IA32_CPU::SHRD_EwGw(Ia32_Instruction_c *i)
{
  Bit16u op1_16, op2_16, result_16;
  Bit32u temp_32, result_32;
  unsigned count;

  if (i->b1() == 0x1ac)
    count = i->Ib();
  else // 0x1ad
    count = CL;

  count &= 0x1f; /* use only 5 LSB's */

  if (i->modC0()) 
  {
    op1_16 = IA32_READ_16BIT_REG(i->rm());
  }
  else 
  {
    read_RMW_virtual_word(i->seg(), IA32_RMAddr(i), &op1_16);
  }

  if (!count) 
	  return;

  op2_16 = IA32_READ_16BIT_REG(i->nnn());

  temp_32 = (op2_16 << 16) | op1_16; // double formed by op2:op1
  result_32 = temp_32 >> count;
  if (count > 16) 
  {
    result_32 |= (op1_16 << (32 - count));
  }
  
  result_16 = result_32;

  if (i->modC0()) 
  {
    IA32_WRITE_16BIT_REG(i->rm(), result_16);
  }
  else 
  {
    write_RMW_virtual_word(result_16);
  }

  set_CF((op1_16 >> (count - 1)) & 0x01);
  set_ZF(result_16 == 0);
  set_SF(result_16 >> 15);
  set_AF(0);

  if (count == 1)
    set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
  set_PF_base((Bit8u) result_16);
}

void IA32_CPU::ROL_Ew(Ia32_Instruction_c *i)
{
  Bit16u op1_16, result_16;
  unsigned count;

  if ( i->b1() == 0xc1 )
    count = i->Ib();
  else if ( i->b1() == 0xd1 )
    count = 1;
  else // 0xd3
    count = CL;

  if (i->modC0()) 
  {
    op1_16 = IA32_READ_16BIT_REG(i->rm());
  }
  else 
  {
    read_RMW_virtual_word(i->seg(), IA32_RMAddr(i), &op1_16);
  }

  if ( (count & 0x0f) == 0 ) 
  {
    if ( count & 0x10 ) 
	{
      unsigned bit0 = op1_16 & 1;
      set_CF(bit0);
    }
    return;
  }
  count &= 0x0f; // only use bottom 4 bits

  result_16 = (op1_16 << count) | (op1_16 >> (16 - count));

  if (i->modC0()) 
  {
    IA32_WRITE_16BIT_REG(i->rm(), result_16);
  }
  else 
  {
    write_RMW_virtual_word(result_16);
  }

  bx_bool temp_CF = (result_16 & 0x01);
  set_CF(temp_CF);
  set_OF(temp_CF ^ (result_16 >> 15));
}

void IA32_CPU::ROR_Ew(Ia32_Instruction_c *i)
{
  Bit16u op1_16, result_16;
  unsigned count;

  if ( i->b1() == 0xc1 )
    count = i->Ib();
  else if ( i->b1() == 0xd1 )
    count = 1;
  else // 0xd3
    count = CL;

  if (i->modC0()) 
  {
    op1_16 = IA32_READ_16BIT_REG(i->rm());
  }
  else 
  {
    read_RMW_virtual_word(i->seg(), IA32_RMAddr(i), &op1_16);
  }

  if ( (count & 0x0f) == 0 ) 
  {
    if ( count & 0x10 ) 
	{
      unsigned MSB = op1_16 >> 15;
      set_CF(MSB);
    }
    return;
  }

  count &= 0x0f;  // use only 4 LSB's
  result_16 = (op1_16 >> count) | (op1_16 << (16 - count));

  if (i->modC0()) 
  {
    IA32_WRITE_16BIT_REG(i->rm(), result_16);
  }
  else 
  {
    write_RMW_virtual_word(result_16);
  }
  
  bx_bool result_b15 = (result_16 & 0x8000) != 0;
  set_CF(result_b15);
  if (count == 1)
    set_OF(((op1_16 ^ result_16) & 0x8000) > 0);

}

void IA32_CPU::RCL_Ew(Ia32_Instruction_c *i)
{
  Bit16u op1_16, result_16;
  unsigned count;

  if ( i->b1() == 0xc1 )
    count = i->Ib();
  else if ( i->b1() == 0xd1 )
    count = 1;
  else // 0xd3
    count = CL;

  count = (count & 0x1f) % 17;
  if (i->modC0()) 
  {
    op1_16 = IA32_READ_16BIT_REG(i->rm());
  }
  else 
  {
    read_RMW_virtual_word(i->seg(), IA32_RMAddr(i), &op1_16);
  }

  if (!count) 
	  return;

  if (count==1) 
  {
    result_16 = (op1_16 << 1) | getB_CF();
  }
  else 
	  if (count==16) 
	  {
		 result_16 = (getB_CF() << 15) | (op1_16 >> 1);
	  }
	  else 
	  { // 2..15
		result_16 = (op1_16 << count) | (getB_CF() << (count - 1)) | (op1_16 >> (17 - count));
	  }

  if (i->modC0()) 
  {
    IA32_WRITE_16BIT_REG(i->rm(), result_16);
  }
  else 
  {
    write_RMW_virtual_word(result_16);
  }

  bx_bool temp_CF = (op1_16 >> (16 - count)) & 0x01;
  set_CF(temp_CF);
  set_OF(temp_CF ^ (result_16 >> 15));

}

void IA32_CPU::RCR_Ew(Ia32_Instruction_c *i)
{
  Bit16u op1_16, result_16;
  unsigned count;

  if ( i->b1() == 0xc1 )
    count = i->Ib();
  else if ( i->b1() == 0xd1 )
    count = 1;
  else // 0xd3
    count = CL;

  count = (count & 0x1f) % 17;

  if (i->modC0()) 
  {
    op1_16 = IA32_READ_16BIT_REG(i->rm());
  }
  else 
  {
    read_RMW_virtual_word(i->seg(), IA32_RMAddr(i), &op1_16);
  }

  if (! count) 
	  return;

  result_16 = (op1_16 >> count) | (getB_CF() << (16 - count)) | (op1_16 << (17 - count));

  if (i->modC0()) 
  {
    IA32_WRITE_16BIT_REG(i->rm(), result_16);
  }
  else 
  {
    write_RMW_virtual_word(result_16);
  }

  set_CF((op1_16 >> (count - 1)) & 0x01);
  if (count == 1)
    set_OF(((op1_16 ^ result_16) & 0x8000) > 0);
}

void IA32_CPU::SHL_Ew(Ia32_Instruction_c *i)
{
  Bit16u op1_16, result_16;
  unsigned count;

  if ( i->b1() == 0xc1 )
    count = i->Ib();
  else if ( i->b1() == 0xd1 )
    count = 1;
  else // 0xd3
    count = CL;

  count &= 0x1f; /* use only 5 LSB's */
  if (i->modC0()) 
  {
    op1_16 = IA32_READ_16BIT_REG(i->rm());
  }
  else 
  {
    read_RMW_virtual_word(i->seg(), IA32_RMAddr(i), &op1_16);
  }

  if (!count) 
	  return;

  result_16 = (op1_16 << count);

  if (i->modC0()) 
  {
    IA32_WRITE_16BIT_REG(i->rm(), result_16);
  }
  else 
  {
    write_RMW_virtual_word(result_16);
  }

  IA32_SET_FLAGS_OSZAPC_16(op1_16, count, result_16, IA32_INSTR_SHL16);
}

void IA32_CPU::SHR_Ew(Ia32_Instruction_c *i)
{
  Bit16u op1_16, result_16;
  unsigned count;

  if ( i->b1() == 0xc1 )
    count = i->Ib();
  else if ( i->b1() == 0xd1 )
    count = 1;
  else // 0xd3
    count = CL;

  count &= 0x1f; /* use only 5 LSB's */

  if (i->modC0()) 
  {
    op1_16 = IA32_READ_16BIT_REG(i->rm());
  }
  else 
  {
    read_RMW_virtual_word(i->seg(), IA32_RMAddr(i), &op1_16);
  }

  if (!count) 
	  return;

#if defined(IA32_HostAsm_Shr16)
  Bit32u flags32;
  asmShr16(result_16, op1_16, count, flags32);
  IA32_setEFlagsOSZAPC(flags32);
#else
  result_16 = (op1_16 >> count);
  IA32_SET_FLAGS_OSZAPC_16(op1_16, count, result_16, IA32_INSTR_SHR16);
#endif

  if (i->modC0()) 
  {
    IA32_WRITE_16BIT_REG(i->rm(), result_16);
  }
  else 
  {
    write_RMW_virtual_word(result_16);
  }

}

void IA32_CPU::SAR_Ew(Ia32_Instruction_c *i)
{
  Bit16u op1_16, result_16;
  unsigned count;

  if ( i->b1() == 0xc1 )
    count = i->Ib();
  else if ( i->b1() == 0xd1 )
    count = 1;
  else // 0xd3
    count = CL;

  count &= 0x1f;  /* use only 5 LSB's */

  if (i->modC0()) 
  {
    op1_16 = IA32_READ_16BIT_REG(i->rm());
  }
  else 
  {
    read_RMW_virtual_word(i->seg(), IA32_RMAddr(i), &op1_16);
  }

  if (!count) 
	  return;

  if (count < 16) 
  {
    if (op1_16 & 0x8000) 
	{
      result_16 = (op1_16 >> count) | (0xffff << (16 - count));
    }
    else 
	{
      result_16 = (op1_16 >> count);
    }
  }
  else 
  {
    if (op1_16 & 0x8000) 
	{
      result_16 = 0xffff;
    }
    else 
	{
      result_16 = 0;
    }
  }

  if (i->modC0()) 
  {
    IA32_WRITE_16BIT_REG(i->rm(), result_16);
  }
  else 
  {
    write_RMW_virtual_word(result_16);
  }

  IA32_SET_FLAGS_OSZAPC_16(op1_16, count, result_16, IA32_INSTR_SAR16);
}
